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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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FDCPE_o1: FDCPE port map (o1,test,clock,'0','0','1');
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FDCPE_o2: FDCPE port map (o2,o2_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;o2_D <= ((test AND NOT i3)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT test AND i3));
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FDCPE_test: FDCPE port map (test,test_D,clock,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;test_D <= (i2 AND i1);
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Register Legend:
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP  (Q,D,G,CLR,PRE); 
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